1. Field of the Invention
The invention relates in general to a signal transmission circuit, and more particularly to a signal transmission circuit suitable for DDR.
2. Description of the Related Art
DDR SDRAM is an acronym of double-data-rate synchronous dynamic random access memory. DDR is first proposed by Samsung in 1996, and is a memory specification collaboratively defined by eight manufacturers including NEC, Mitsubishi, Fujitsu, Toshiba, Hitachi, TI, Samsung and Hyundai. DDR also gained supported from main chipset manufacturers including AMD, VIA and SiS. Being an upgrade version of the common SDRAM, DDR is also referred to as SDRAM II. One critical feature of the DDR technology is that, data can be transmitted at rising edges and falling edges of clocks, and so the data transmission speed can be doubled without changing the clock rate. As such, DDR is extensively applied in various signal processing systems.
In general, an integrated circuit is roughly divided into a core portion and an input and output (IO) portion. The IO portion bridges the communication to the external for the core portion. In addition to transmitting core signals generated by the core portion to outside the integrated circuit via a connecting pad, the IO portion also needs to transmit external signals sent from the external to the connecting pad further to the core portion for processing. It is required that the operating voltage of the core portion be reduced with demands of the increasing operating speed and power saving effect of electronic products. Similarly, to increase the transmission efficiency of external signals between integrated circuits, the driving voltage of new-generation external signals is also lowered. Take a double-data-rate three synchronous dynamic random access memory (DDR3 SDRAM) for example. The specified operating voltage of the DDR3 SDRAM is 1.5V, whereas the operating voltages of the DDR1 and DDR2 SDRAMs are 2.5V and 1.8V, respectively. In the latest DDR4, the operating voltage is reduced to even as low as 1.2V.
Two devices can be manufactured from a semiconductor wafer by a conventional semiconductor manufacturing process—a core device and an IO device. Generally, core devices have a faster speed and a stronger driving capability but can withstand a lower voltage difference. That is, all conducting ends (e.g., the gate, source and drain) of a core device can have a lower voltage difference, e.g., 1.1V. On the other hand, IO devices have a slower speed and a weaker driving capability but can withstand a greater voltage difference. That is, all conducting ends (the gate, source and drain) of an IO device can have a greater voltage difference, e.g., 1.5V. For example, when the IO device and the core device are both MOS devices, the gate oxidation layer in the IO device is thicker than the gate oxidation layer in the core device, such that the IO device has better robustness for withstanding higher voltage stress.
FIG. 1 shows a current signal transmission circuit 10 suitable for DDR, e.g., DDR3, to transmit high-speed clock signals or data signals. As shown in FIG. 1, the current signal transmission circuit 10 drives a connecting pad 15, and includes a level shifting circuit 11, a buffer circuit 12 and an output circuit 13. The output circuit 13 includes a pull-up circuit 13a and a pull-down circuit 13b. The buffer circuit 12 includes an up buffer unit 12a and a down buffer unit 12b, and the level shifting circuit 11 includes an up level shifter 11a and a down level shifter 11b. The up level shifter 11a and the down level shifter 11b of the level shifting circuit 11 receive an input signal IN. For example, the input signal IN is a square-wave signal formed by a first operating voltage Vsscore and a second operating voltage Vddcore, e.g., a square-wave signal formed by 0V and 1.1V. Components in the signal transmission circuit 10 are all implemented by IO devices. For example, inverters in the up level shifter 11a, the down level shifter 11b, the up buffer unit 12a and the down buffer unit 12b are all disposed between an operating voltage Vddio (1.5V) and a ground voltage Vssio (0V), and a pull-up transistor PMOS T1 and a pull-down transistor NMOS 13a in the pull-up circuit 13a and the pull-down circuit 13b are capable of withstanding a 1.5V voltage difference (Vddio−Vssio). Further, the voltage difference between two operating voltages of the input signal IN corresponds to the output of the core circuit, and is usually smaller, e.g., smaller than the DDR3 operating voltage Vddio (1.5V). In the signal output circuit 10, a pull-up transistor PMOS and a pull-down transistor NMOS in the pull-up circuit 13a and the pull-down circuit 13b are implemented by IO devices having weaker capabilities. That is, to satisfy DDR3 driving specifications, an extremely large semiconductor area is required.
The signal transmission circuit may also reduce the required semiconductor area by adopting core devices. FIG. 2 shows another current output circuit 23 for replacing the output circuit 13 in FIG. 1. Pull-up transistors PMOS PH1 and PH2 and pull-down transistors NMOS NL1 and NL2 in the output circuit 23 are implemented by core devices. The gate of the pull-up transistor PMOS PH1 receives a logic signal Sp having high and low logic levels of 1.5V and 0.4V, respectively, and the gate of the pull-up transistor PMOS PH2 is connected to a reference voltage having a voltage of 0.4V. The gate of the pull-down transistor NMOS NL2 receives another reference voltage Vbn having a voltage of 1.1V, and the gate of the pull-down transistor NMOS NL1 receives another logic signal Sn having high and low logic levels of 1.1V and 0V, respectively. The high logic level refers to a voltage level of a signal when the signal is at logic “1”, and the low logic level refers to a voltage level of a signal when the signal is at logic “0”. The pull-up transistors PMOS PH1 and PH2 are connected in series, and the pull-down transistors NL1 and NL2 are connected in series. Such series connection prevents the core devices (pull-up transistors T1 and T2 and pull-down transistors T3 and T4) operating at a 1.1V operating voltage from damages caused by higher operating voltages (e.g., 1.5V).
However, in the output circuit 23, between the gates of the pull-up transistor PMOS PH2 and the pull-down transistor NMOS NL2 and the connecting pad 24 is an extremely large parasitic capacitance. To prevent unstable signals of the reference voltages Vbp and Vpn received at the gates of the pull-up transistor PMOS PH2 and the pull-down transistor NMOS NL2, very large decoupling capacitors C1 and C2 need to be connected to the gates of the pull-up transistor PMOS PH2 and the pull-down transistor NMOS NL2, respectively, to eliminate or alleviate the effects that the signal change at the connecting pad 24 has on the reference voltages Vbp and Vbn. The decoupling capacitors C1 and C2 may further occupy a substantial semiconductor area.
Therefore, there is a need for a signal transmission circuit suitable for DDR to solve the above issues.